In general, aluminum and silicon oxide have been widely used for interconnections of semiconductor devices and inter-metal dielectrics (IMDs), respectively.
To achieve high speed and high integration of semiconductor devices, recently there has been great progress in the study of copper, which exhibits a lower electric resistance than aluminum, and low k-dielectric, which has a lower dielectric constant than the silicon oxide.
Copper exhibits electric resistance of 1.70×10−6 Ωcm, which is lower than aluminum, which exhibits electric resistance of 2.74×10−6 Ωcm. Also, copper has attracted attention as a material that may solve electromigration (EM) suffered by aluminum. However, copper formerly could not be used in existing vapor deposition and dry etching processes. But now, it has become possible to utilize copper for interconnections of semiconductor devices through recently proposed electroplating and dual damascene processes.
Use of the low k-dielectric layer may minimize an increase in RC delay times and cross-talk characteristics, which are caused by a reduction in distance between interconnections due to the high integration of semiconductor devices. Thus, a material such as SiOC, SOG, or porous dielectric, of which the dielectric constant (3.0 or less) is lower than that (3.9 to 4.2) of the silicon oxide layer, have been discussed for the low k-dielectric layer.
FIGS. 1A through 1C are cross-sectional views illustrating the conventional dual damascene method using the low k-dielectric layer for an inter-metal dielectric layer. The conventional dual damascene process is commonly called a “Via first approach technique.”
Referring to FIG. 1A, a lower interconnection 15 is formed on a semiconductor substrate. A lower etch stop layer 20, a lower dielectric layer 25, an upper etch stop layer 30, and an upper dielectric layer 35 are sequentially stacked on the entire surface of the semiconductor substrate including the lower interconnection 15. The upper dielectric layer 35, the upper etch stop layer 30, and the lower dielectric layer 25 are successively patterned to form a via hole 40, which exposes the upper side of the lower etch stop layer 20. Here, as described above, the upper and lower dielectric layers 35 and 25 are formed of low k-dielectric layers such as SiOC, SOG, and porous dielectric.
Referring to FIG. 1B, photoresist is formed to fill the via hole 40 on the entire surface of the semiconductor substrate where the via hole 40 is formed. The photoresist is exposed and developed to form a photoresist pattern 50, which will serve as a mask during a subsequent process of patterning the upper dielectric layer 35. For this, the photoresist pattern 50 crosses over the via hole, exposing the upper dielectric layer 35.
During the exposure process, the photoresist, which contacts the upper and lower dielectric layers 35 and 25, causes an abnormal reaction. That is, the photoresist residue 99, which is not removed by the development process, is formed. As a result, the photoresist residue 99 covers the inner wall of the via hole 40 and occasionally covers the upper side of the upper dielectric layer 35 around the via hole.
The abnormal reaction results from reaction of basic materials included in the upper and lower dielectric layers 35 and 25 formed of low k-dielectric layers with hydrogen ions produced from the exposure process. The basic materials are produced as a result of penetration of nitrogen atoms used during processes of forming the via hole 40, removing the photoresist, and cleaning, into the upper and lower dielectric layers 35 and 25. Also, the hydrogen ions are generated during an ultraviolet photolithographic process (in more detail, an exposure process) for controlling the development process by using photo-generating acid. The ultraviolet photolithographic process is typically used for highly integrated semiconductor devices requiring the low k-dielectric layers.
Referring to FIG. 1C, an anisotropic etching process is carried out using the photoresist pattern 50 as an etch mask, thereby etching the upper dielectric layer 35 and the upper etch stop layer 30. Thus, an upper dielectric pattern 36 and an upper etch stop pattern 31 are formed to expose the upper side of the lower dielectric layer 25. Here, even though it is preferable to expose a top surface of the lower interconnection 15, the lower interconnection 15 is not exposed due to the photoresist residue 99, which serves as an etch stop layer.
As illustrated in FIG. 1B, the photoresist residue 99 covers the upper side of the upper dielectric layer 35 around the via hole 40. As a result, the upper insulation spacer 37 may remain on the upper etch stop layer 30 around the via hole 40, even after the process of forming the upper dielectric pattern 36. The photoresist residue 99 and the upper insulation spacer 37 may cause the lower interconnection 15 to be opened.
FIGS. 2A and 2B are cross-sectional views illustrating another problem of the conventional dual damascene process. In general, a single upper interconnection is connected with a plurality of via holes 40, which may be spaced apart from each other by a narrow interval. FIGS. 2A and 2B illustrate cross-sections of a narrow region between the via holes. Steps of FIGS. 2A and 2B are the same as those of FIGS. 1A through 1C. A description of the same steps will be omitted here to avoid redundancy.
Referring to FIGS. 2A and 2B, when the via hole 40 is formed as illustrated in FIG. 1A, the upper edge of the upper dielectric layer 35 may be rounded. Such a problem occurs because the via hole 40, which penetrates the upper dielectric layer 35, the upper etch stop layer 30, and the lower dielectric layer 25, is deep. To undergo a stable photolithographic process, another photoresist pattern (not shown) for forming the via hole 40 has a predetermined thickness. As a result, another photoresist pattern is worn out during the etching process for forming the deep via hole 40 so as to both cause the edge of the upper dielectric layer 35 to be rounded (or recessed), and allow the inner wall of the via hole 40 to be slanted, as illustrated in FIGS. 2A and 2B. The round shape of the upper dielectric layer 35 is transferred to the upper edge of the lower dielectric layer 25 during the etching process for forming the upper dielectric pattern 36. Thus, the upper side of the lower dielectric layer 25 is recessed between the adjacent via holes, thus becoming reduced in thickness as shown at 88, such that the height of the top surface is reduced. Such a problem (88) causes a subsequent process of forming an upper interconnection (not shown) to be unstable.
Furthermore, according to the conventional method, the thickness of the upper dielectric layer 30 is formed in consideration of the recess formed during a subsequent planarizing etch process for forming the upper interconnection. However, in the case that the upper dielectric layer 35 is thickly formed in consideration of the recess, when the photolithographic process for forming the via hole 40 is carried out, the photoresist layer should be thicker to minimize the problems caused by the consumption of the photoresist. However, if the photoresist becomes thick, the photolithographic process becomes difficult, as described above.